Thin-film resistor layout
US5218225A · kind A · utility
13Cited by
10References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Mar 30, 1990 |
| Grant date | Jun 8, 1993 |
| Priority date | — |
| Expiry date | Mar 30, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A class of layout patterns for variable resistors and integrated circuits where the resistance is varied by varying a wiping point on a resistor line; contact is not made into the resistor line itself, but instead all contacts are made only to tabs which extend out from the resistor line. Preferred embodiments use a meander resistor line made of polysilicon within a silicon integrated circuit. Simple processing mask modifications can be used to change the geometry of the meander line to vary the resistance. The wiping point is digitally selected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.