Multistep analog-to-digital converter with embedded correction data memory for trimming resistor ladders
US5218362A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 2, 1992 |
| Grant date | Jun 8, 1993 |
| Priority date | — |
| Expiry date | Jul 2, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/145
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog-to-digital converter (ADC) has at least one resistance ladder circuit for generating a stepped series of reference voltages and set of comparator circuits for comparing an input voltage, or a voltage derived therefrom, with at least a subset of the stepped series of reference voltages. A memory array embedded in the ADC stores a digital value corresponding to each tap point of the resistance ladder and thus to each reference voltage. During a first conversion cycle an estimated conversion value is generated based on comparison of the input voltage with the stepped series of reference voltages. The estimated conversion value corresponds to one of the resistor ladder tap points selected as being closest in voltage to the input voltage. In a second conversion cycle, a derived voltage based on the input voltage of the estimated conversion value, is compared with a smaller range of reference voltages to generate a finer resolution conversion value. In accordance with the present invention, the voltage on one of the two input nodes of the comparators used in the second conversion cycle is adjusted by an amount proportional to the digital value, stored in the ADC's embedded memo…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.