Interprocessor switching network
US5218602A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 1991 |
| Grant date | Jun 8, 1993 |
| Priority date | — |
| Expiry date | Apr 4, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/563
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital switching network for providing simultaneous connections among user processors of processor-based communications equipment. The user processors act as originators and destinations of data communications packets. Packet data connections are through node controllers, which communicate with gateways, which are connected to a switching network via packet links. Control messages are communicated between node controllers, gateways, and an interchange control subsystem via various control message links. All control message processing and packet data transmissions are synchronized with a packet frame synchronization signal, and processing tasks performed by each of the network subsystems are pipelined so that they occur simultaneously. Service requests are queued in a central queue in the interchange control system. The synchronization and queueing simplify the control messages that are required to set up and release the connections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.