Method and apparatus for changing bit rate of digitized analog
US5218639A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 2, 1991 |
| Grant date | Jun 8, 1993 |
| Priority date | — |
| Expiry date | Dec 2, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H2021/0096
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Method and apparatus for changing the bit rate of a digitized analog signal stream from a first bit rate to a second bit rate. A first sequence generator provides a digital predictor sequence clocked at the first bit rate. A combiner has an output providing a combined digital stream at the first bit rate, combining the digital predictor sequence at the first bit rate and the digital analog signal stream at the first bit rate. An adaptive processor has its input coupled to at the output of the signal combiner. The adaptive processor has variable weights which are responsive to an error signal, an output providing a processed combined digital stream having a bit rate responsive to the weights, and an error signal input port. A second sequence generator provides the same digital predictor sequence, but clocked at the second bit rate. An error detector, coupled to output of the adaptive processor and the digital predictor sequence clocked at the second bit rate, provides an error signal representing the difference between the bit rate of the processed digital sequence and the digital predictor sequence clocked at the second bit rate. The error signal is coupled to the error signal port…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.