Data link controller with autonomous in tandem pipeline circuit elements relative to network channels for transferring multitasking data in cyclically recurrent time slots
US5218680A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 1990 |
| Grant date | Jun 8, 1993 |
| Priority date | — |
| Expiry date | Mar 15, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L69/324
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A "single-chip" integrated circuit device, useful in ISDN digital voice and data telephone applications, links plural channels of a data communication network with memory and CPU components of a data processing system. The device couples to the system via a bus that may be shared by other devices, and bidirectionally exchanges service information signals with the system CPU, and communication data signals with system memory. The service information includes device control information furnished by the CPU, and (channel and device) status information prepared by the device. The device contains multiple logic circuit units, operating in relative functional autonomy, and buffer memory units for storing service information and data. Units which interface to the network operate in synchronism with network communication processes. Units which interface to the system bus operate in asynchronous relation to network processes. Synchronous units which handle data are configured to form plural stage pipelines, in each direction of communication, which eases timing requirements at the bus interface. Status information is stored queued in memory unit storage spaces dedicated to the channels; eac…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.