Circuit configuration and method for priority selection of interrupts for a microprocessor
US5218703A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 20, 1992 |
| Grant date | Jun 8, 1993 |
| Priority date | — |
| Expiry date | Apr 20, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/374
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit configuration and a method for priority selection of interrupts for a microprocessor in an integrated circuit which includes a central processing unit, a central interrupt node connected to the central processing unit, N interrupt sources for presenting interrupt requests to the central processing unit, peripheral interrupt nodes each being connected to a respective one of the N interrupt sources. A common interrupt bus is connected to the peripheral interrupt nodes and to the central interrupt node. The method for priority selection includes activating the interrupt bus in a prioritizing round in accordance with a priority value with a peripheral interrupt node assigned to an interrupt source in the presence of an interrupt request of the interrupt source.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.