High speed bus transceiver with fault tolerant design for hot pluggable applications
US5220211A · kind A · utility
43Cited by
7References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 28, 1991 |
| Grant date | Jun 15, 1993 |
| Priority date | — |
| Expiry date | Oct 28, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/08
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A high-speed data transport system for use in computers, switches, microprocessors or the like includes a low impedance differential bus and a plurality of transceivers connected to the bus. Each of the transceivers is provided with a driver circuit which places data onto the bus and a receiver for accepting data from the bus. The driver includes a pseudo-differential current driving circuit arrangement which sinks current from only one side of the bus while the other side of the differential bus is undisturbed. The receiver includes a differential comparator biased to a preferred output voltage level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.