Neural net architecture for rate-varying inputs
US5220640A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 20, 1990 |
| Grant date | Jun 15, 1993 |
| Priority date | — |
| Expiry date | Sep 20, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG10L15/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A neural net architecture provides for the recognition of an input signal which is a rate variant of a learned signal pattern, reducing the neural net training requirements. The duration of a digital sampling of the input signal is scaled by a time-scaling network, creating a multiplicity of scaled signals which are then compared to memorized signal patterns contained in a self-organizing feature map. The feature map outputs values which indicate how well the scaled input signals match various learned signal patterns. A comparator determines which one of the values is greatest, thus indicating a best match between the input signal and one of the learned signal patterns.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.