Parallel data processing apparatus with signal skew compensation
US5220660A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 27, 1991 |
| Grant date | Jun 15, 1993 |
| Priority date | — |
| Expiry date | Jun 27, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A parallel data processing apparatus including a plurality of processors, a pair of signal paths are provided for each processor, one signal path of each pair being used for supplying a predetermined signal to the processor, and the second signal path being used for returning the signal from the processor to a predetermined position common to all of the processors. Each of the above signal paths include a variable delay unit. The apparatus further includes a delay measuring unit for measuring the time elapsing while the signal is propagated from the above predetermined position to a corresponding processor and then returned from the processor to the above predetermined position through each pair of signal paths. Further the apparatus includes a delay adjusting unit for adjusting the delays caused by the variable delay units in all of the signal paths. The delay adjustment are based on the results of a measurement by the delay measuring unit, so that the time elapsing while the signal is propagated from the predetermined position to the plurality of processors, through the respective signal paths for supplying the signal to the processors, are equal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.