Logic equation fault analyzer
US5220662A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 1991 |
| Grant date | Jun 15, 1993 |
| Priority date | — |
| Expiry date | Mar 28, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0724
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In order to provide the facility in an information processing system to analyze system faults which result in the setting of one or more flags, a logic equation fault analyzer utility program is used. In the exemplary implementation, the fault flags are the symbols, and the combinations of symbols which make up a specific fault event can be expressed in terms of a logic equation. A logic equation is written for each of all known fault events which may occur in a given system, and these logic equations are placed in a table on a prioritized basis. It will then be the responsibility of the logic equation fault analyzer to identify the first equation in the table which matches the input symbols. In addition the logic equation fault analyzer must identify those symbols which are not part of the equation so that these symbols may be analyzed separately at a later time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.