Processor controlled command port architecture for flash memory
US5222046A · kind A · utility
150Cited by
9References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 19, 1990 |
| Grant date | Jun 22, 1993 |
| Priority date | — |
| Expiry date | Oct 19, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/32
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor flash EPROM/EEPROM device which includes a command port controller for receiving command instructions from a data bus coupled to the memory device. Instruction words to a command port controller operates to instruct the device to perform read, erase, program, or verify functions and the command port controller generates necessary control signals to cause the memory to function appropriately. By utilizing the command port controller the memory device can be erased and programmed while the device is in the circuit and permits pin compatibility with the prior art EPROM and EEPROMs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.