Method and circuit arrangement for reducing the loss of message packets that are transmitted via a packet switching equipment
US5222063A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 1991 |
| Grant date | Jun 22, 1993 |
| Priority date | — |
| Expiry date | Apr 1, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/555
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
For reducing the loss of message packets that are transmitted according to an asynchronous transfer mode during the course of virtual connections and which comprise a packet header identifying the respective virtual connection and that are respectively augmented by a sequential auxiliary identifier and that, after multiplication, or transmitted separately via redundant switching matrices of a packet switching equipment, message packets that follow a respective faulty-transmitted message packet are intermediately stored, and that, following the transmission of an error-free message packet which corresponds to the respective faulty-transmitted message packet via a switching matrix that respectively transmits more slowly, the intermediately-stored message packets are forwarded in rapid succession.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.