Patent · US Expired

Electronic counter for counting periodic clock signal generated at preset clock frequency

US5222110A · kind A · utility

9Cited by
4References
8Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 31, 1992
Grant dateJun 22, 1993
Priority date
Expiry dateJan 31, 2012

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F7/68
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

The electronic counter for counting a periodic clock signal generated at a preset clock frequency (f.sub.o) includes a clock circuit generating the periodic clock signal at the preset clock frequency (f.sub.o); an adjustable frequency divider (4) having an output (8), a first input (5) and a second input (7), the first input of the frequency divider (4) being connected to the clock circuit (6) so as to receive the periodic clock signal and the second input (7) of the frequency divider being connected to receive a cycle speed signal (n), the frequency divider (4) containing means to produce a pulsed output signal at a divider output frequency (c.sub.o); a tracking circuit (T) connected to the output (8) of the frequency divider (4) to receive the pulsed output signal at the divider output frequency (c.sub.o) and having a correction signal input for receiving a positive or negative correction signal (KS), the tracking circuit (T) acting to add a number of additional pulses to the pulsed output signal received thereby when the correcting signal is positive and suppressing a number of the pulses of the pulsed output signal from the frequency divider when the correcting signal is negati…

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.