Pipeline computer system having write order preservation
US5222219A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 27, 1990 |
| Grant date | Jun 22, 1993 |
| Priority date | — |
| Expiry date | Aug 27, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/36
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for preserving data transfer order in a pipeline computer system, wherein a first block of data is transferred from a first device to at least a second device during a first computer cycle. Simultaneously, the first block of data is stored within the first device. Druing a second computer cycle, a second block of data is transferred from the first device to the second device, and an acknowledge signal is issued, indicating the success or failure of the transfer of the first block of data. If the acknowledge signal indicates a failed data transfer, a reject signal is issued and data transfer is restarted beginning with the previously failed data transaction which has been stored within the first device, and data transfer then continues with a preserved data transfer order.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.