Method and apparatus for implementing a concurrent logic program
US5222221A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 16, 1992 |
| Grant date | Jun 22, 1993 |
| Priority date | — |
| Expiry date | Jan 16, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4496
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A flat concurrent Prolog (Fcp) computer comprises a memory in which all the data is stored, three sets of registers, several queues or lists and a computer program for controlling the computer. The memory is a single data area called the "heap" which also includes two small data areas called the "trail" and the suspension table as well as the queues. The queues include the resolvent which is also called the active queue or the process queue, the activation queue, the process free list and the suspension free list. The registers include a set of general registers, a set of procedure try registers and a set of clause try registers. The general registers include a heap backtrack register, a queue front register, a queue back register, a process free list register, and a suspension free list register. The procedure try registers include a current process register, a time slice register that identifies the number of process iterations that can be done, a program counter, a failure label register that contains the address of the first instruction in the next clause to be tried, and a suspension table pointer. The clause try registers include a heap pointer register, an activation pointer…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.