Multiprocessor system having synchronization control mechanism
US5222229A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 1990 |
| Grant date | Jun 22, 1993 |
| Priority date | — |
| Expiry date | Mar 9, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/167
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A synchronization controller is provided for each processor in a multiprocessor system. The synchronization controllers are commonly connected to a synchronization signal bus. Each of the synchronization controllers has a synchronization wait signal transmitting means for receiving a synchronization request signal from a corresponding processor, signal means for transmitting a synchronization wait signal to the synchronization signal bus, a synchronization register for specifying the other processors to be synchronized with the corresponding processor, a comparator means for comparing the signal from the synchronization signal bus with the content of the synchronization resister, and a means for transmitting to the corresponding processor a synchronization-acknowledge signal based on the result of comparison by the comparator means.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.