Method and apparatus for delaying writing back the results of instructions to a processor
US5222240A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1990 |
| Grant date | Jun 22, 1993 |
| Priority date | — |
| Expiry date | Feb 14, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention describes an integer execution unit register file having one fewer write port by employing delayed writeback for data transfer instructions in a high speed processor. The integer execution unit comprises a register file with 32 separate registers, each 32-bits long. The register file is a write through register file. A four-stage instruction pipeline is employed to execute all integer instructions. The four stages are (1) Fetch, (2) Decode, (3) Execute, and (4) Writeback. For data transfer type of instructions such as, a load instruction, one extra instruction stage is usually required. The prior art processors add one extra write port to accommodate such data transfer type of instructions. The present invention delays the writing of the data transfer type instruction until the writeback stage of the next data transfer instruction. The result of the data transfer type instruction returns at the end of the writeback stage. The result is held in a temporary register. All references to the result of such a data type transfer instruction will be bypassed from the temporary register to the proper execution block. The data from the temporary register is written back…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.