DRAM-cell having an isolation merged trench and its method of manufacture
US5223447A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 1990 |
| Grant date | Jun 29, 1993 |
| Priority date | — |
| Expiry date | Sep 4, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/68
Abstract
A method for manufacturing a DRAM cell is provided having an isolation merged trench for applying to 16 megabit and 64 megabit DRAM cells, which includes the steps forming a primary dielectric for a capacitor within the interior of a trench, depositing an n.sup.+ doped polysilicon, forming a secondary dielectric and then stacking polysilicon thereon and connecting the polysilicon within an n.sup.+ diffusion layer of the bottom of the trench for forming a plate. As a result of this method all of the capacitors disposed between the n.sup.+ polysilicon storing electrode and the n.sup.+ polysilicon plate as well as the polysilicon storing electrode and the n.sup.+ diffusion layer plate are utilized as a storing capacitor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.