Power down Miller Killer circuit
US5223745A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 14, 1992 |
| Grant date | Jun 29, 1993 |
| Priority date | — |
| Expiry date | Aug 14, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/01721
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit to be used with bistate and tristate output buffers as a means of diverting from the output pulldown transistor Miller Current arising while the output buffer is powered down. Its purpose is to avoid loading the common bus to which the output buffer is attached, in particular under the circumstances where other output buffers on the bus are causing transitions to occur and the buffer of interest has been powered down. In its preferred embodiment the invention utilizes a MOS transistor coupled between the output pulldown transistor and the lower potential power rail of the output buffer. This MOS transistor is controlled by another MOS transistor coupled to output V.sub.OUT of the buffers. This driver transistor is controlled by the high potential power rail of the buffer and so turns on the Miller Current Discharge Transistor only when the buffer is powered down. The invention also encompasses a discharge transistor coupled to the data input V.sub.IN to ensure that the Miller Current Discharge Transistor never pulls the of the output pulldown when the buffer is in its active low state.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.