Manufacturing method of self-aligned GaAs FET using refractory gate of dual structure
US5225360A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 26, 1991 |
| Grant date | Jul 6, 1993 |
| Priority date | — |
| Expiry date | Dec 26, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/28587
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is disclosed a manufacturing method of self-aligned GaAs FET using refractory gate with dual structure, the manufacturing method of the invention comprising the steps of: forming first photoresist pattern on a GaAs substrate to define an active region and ion-implanting n type impurity in the active region of the GaAs substrate; sequentially depositing a nitrogen-containing silicon layer and a metal layer on the substrate after removal of the first photoresist pattern; forming second photoresist pattern on the metal layer to define a gate; removing the silicon and metal layers using the second photoresist pattern as a gate mask to form the gate with dual structure of the silicon and metal layers; forming third photoresist pattern on the substrate to define source/drain regions after removal of the second photoresist pattern, and ion-implanting high-density impurity in the source/drain regions using the third photoresist pattern and the gate as a source/drain mask; annealing the substrate to make the silicon layer as upper side of the gate into metal-silicon-nitride material, and to make bottom portion of the metal layer as lower side of the gate into metal-silicon-nitride mat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.