CMOS gate array configured as a SRAM with load resistors over gate electrodes

US5225693A · kind A · utility

Assignee

• SONY GROUP CORPORATION · JP

Inventor

• Teruo Hirayama · Fukuoka, JP

Key dates

• Filing date: Feb 8, 1991
• Grant date: Jul 6, 1993
• Expiry date: Feb 8, 2011

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S257/904

Abstract

In a semiconductor memory serving as an SRAM mounted on a CMOS gate array, a memory cell is constituted by a pair of transistors of a first conductivity type channel and a pair of transistors of a second conductivity type channel of the CMOS gate array and load resistances formed on the gate electrodes of the pair of transistors of the first conductivity type channel. Although the CMOS gate array is used, a memory cell area is small and a large capacity can be easily obtained.