Semiconductor integrated circuit device
US5225720A · kind A · utility
15Cited by
5References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 3, 1991 |
| Grant date | Jul 6, 1993 |
| Priority date | — |
| Expiry date | Oct 3, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Variable current sources (10a-10c) limit a value of current in each of standard cells (2a-2c) depending on a bias voltage given from a bias voltage generating circuit (11) whereby driving capability of each standard cell is limited. As a result, in both cases where the maximum load capacitance in practice is smaller than the load capacitance assumed at the time of designing, and where each standard cell is operated at a lower operation speed than the speed assumed at the time of designing, waste of power consumption can be avoided and noise can be reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.