Velocity-modulation transistor with quantum well wire layer
US5225895A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1990 |
| Grant date | Jul 6, 1993 |
| Priority date | — |
| Expiry date | Dec 12, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/43
- WIPO fieldMicro-structural and nano-technology
- WIPO sectorChemistry
Abstract
An electron supply layer, a quantum well layer, a first barrier layer, a quantum well layer and a second barrier layer are formed in that order on a GaAs substrate to obtain a device, and source, drain and gate electrodes are provided on the surface of this device. In the above described quantum well layers, the lowest sub-band energies of respective carriers largely differ from each other. Accordingly, one of the above quantum well layers serves as a high-speed channel, and the other serves as a low-speed channel. The change in current value with the application of a gate bias depends only on the speed at which electrons move from the high-speed channel to the low-speed channel. Consequently, a velocity-modulation transistor can be constructed which operates at substantially high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.