Integrated data processor having mode control register for controlling operation mode of serial communication unit
US5226173A · kind A · utility
9Cited by
13References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 13, 1992 |
| Grant date | Jul 6, 1993 |
| Priority date | — |
| Expiry date | Mar 13, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reception unit for providing data supplied from a serial input circuit to an inner bus and a transmission unit for providing the data supplied from the inner bus to a serial output circuit hold at least two types of control procedures selected from HDLC procedure, BI-SYNC procedure and start-stop synchronous procedure as control procedures for data transmission/reception, and the control procedures held by these units can be selected alternatively based on a mode control data written in a mode control register by a processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.