Method for fabricating non-volatile memory cells, arrays of non-volatile memory cells

US5227326A · kind A · utility

Assignee

• TEXAS INSTRUMENTS INCORPORATED · US

Inventor

• Kevin Walker · Sheffield, GB

Key dates

• Filing date: Jun 3, 1992
• Grant date: Jul 13, 1993
• Expiry date: Jun 3, 2012

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B41/49

Abstract

The method is provided for selectively fabricating erasable read-only memory and read-only memory cells at a face of a layer of semiconductor of a first conductivity type. Active areas on the face of the layer of semiconductor are selectively defined by masking the face of the layer of semiconductor and patterning and etching the mask to expose first and second areas of the layer of semiconductor. A layer of conductor is formed insulatively adjacent the active area of each cell being fabricated. The layer of conductor is patterned and etched to define a first level gate conductor adjacent at least a portion of the active area of each cell being fabricated, the first level gate of each read-only memory cell set to a logic zero being fabricated disposed adjacent a one of the insulator regions adjacent a corresponding one of the third exposed areas. A layer of interlevel insulator is formed adjacent the first level gate of each erasable read-only memory cell being fabricated. A second layer of conductor is formed adjacent the layer of interlevel insulator of each erasable memory cell being fabricated. The second layer of conductor, the layer of interlevel insulator, and the first leve…