Cascaded drive units having low power consumption
US5227790A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 1992 |
| Grant date | Jul 13, 1993 |
| Priority date | — |
| Expiry date | Jan 24, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A drive device with a data latch circuit which is formed of a plurality of latches, which successively latch serial drive data and output them in parallel, and a shift register having a plurality of first flip-flops which provide, responsive to clock pulses, latch signals for causing the latch to latch the serial data in succession. In one aspect of the invention, the shift register also outputs an end signal when output of the latch signals is completed, and a gate circuit which blocks input of the serial data to the data latch circuit responsive to the end signal. In another aspect of the invention, the shift register has a second flip-flop which produces an output signal after output of the latch signals to said plurality of latches is completed, and a logic gate circuit receiving a latch complete signal that is output from one of the first flip-flops upon completion of the output of the latch signals, and the output signal from the second flip-flop, and outputs a signal of the predetermined level for a predetermined period. A blocking circuit blocks the serial data or the clock pulse responsive to an end signal output from the second flip-flop.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.