Method for embodying twin-connection integrated circuits
US5228951A · kind A · utility
2Cited by
1References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 3, 1991 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Oct 3, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/14
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is disclosed for a forming integrated circuit on a semiconductor chip, said semiconductor chip having the first surface having a central region and a peripheral region including forming more than one contact region on each line connecting two active regions of the semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.