Method and apparatus for high speed digital sampling of a data signal
US5229668A · kind A · utility
24Cited by
4References
7Claims
0Family size
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Key dates
| Filing date | Mar 25, 1992 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Mar 25, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A data signal may be sampled at high speed using a clock signal by propagating the data signal and the clock signal through a series of data and clock delay elements, respectively, and latching the corresponding delayed data and clock signals. The sampling speed is thereby controlled by the relative skew between the clock and data signals, which can be made relatively small and may be limited only by noise and random variations in fabrication. Accordingly, high speed sampling may be obtained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.