High order carry multiplexed adder
US5229959A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 1991 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Jan 31, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary adder of the carry multiplex signal selection type wherein multiple levels of multiplexing between parallel carry paths is used to achieve improved adder performance as measured by adder fabrication area requirements and other performance criteria. The resulting adder employs a plurality of different adder stages of successively increasing complexity and achieves performance time that can be characterized as being of the order of Log.sub.2 (n), wherein n represents bit count, and as requiring a gate count that is of the order of n. Both internal arrangement of the adder stages and interconnection arrangements therefor are disclosed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.