Process and circuit arrangement for digital control of the frequency and/or phase of scanning clock pulses
US5230012A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 29, 1989 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Aug 29, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/107
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Scanning samples of digital signals received in analog form are sent at intervals determined by the scanning clock pulses to a digital signal receiving network after analog-digital conversion for conversion of digital signals received in analog form. The respective digital signal receiving unit delivers control signals derived from the received digital signals. After filtering, these control signals are sent at predetermined intervals to a clock generator to deliver the scanning clock pulses. Filtering of the control signals takes place in the form EQU Ta(i)=a1(Te(i)-a2(Te(i-1))+Ta(i-1), where a1 and a2 denote a set of filter coefficients, Ta(i) and Ta(i-1) are filtered control signals at the times i and (i-1) and Te(i) and Te(i-1) are control signals delivered at times i and (i-1). The set of filter coefficients is fixed in accordance with the value of the instantaneous control signal deviation. The filtered control signals are then sent to the clock generator in quantized form.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.