PLL-based precision phase shifting at CMOS levels
US5230013A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 6, 1992 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Apr 6, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15066
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for generating precise, phase shifted, CMOS level output signals with respect to an input data signal has been provided. The circuit utilizes a phase-locked loop for generating a precise clock signal. This precise clock signal is then utilized to clock a plurality of serially-coupled flip-flops wherein two-times the input data signal is applied to the data input of the first serially-coupled flip-flop. The outputs of the serially-coupled flip-flops are ECL signals which are then translated to CMOS level signals via ECL-CMOS translators. Finally, the output signals of the translators are respectively used to clock divide-by-two configured flip-flops in order to provide the plurality of precise, phase shifted CMOS output signals. The plurality of precise, phase shifted, CMOS output signals have a 50% duty cycle and represent phase shifted versions of the input data signal wherein the minimum time delay between signals is substantially equal to the period of the precise clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.