System for independently controlling supply of a clock signal to a selected group of the arithmetic processors connected in series
US5230046A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 1989 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | Oct 10, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a computer system comprising first through K-th arithmetic processors connected to a control section (18) in an ascending order, where K represents a positive integer which is not less than two, a memorizing unit (20) memorizes first and second information. A clock controlling unit (21) detects a fault signal produced by a k-th arithmetic processor, where k represents one of 1 through K. When the memorizing unit memorizes the first information, the controlling unit controls a supplying unit (19) to put the k-th through the K-th arithmetic processors out of operation. When the memorizing unit memorizes the second information, the controlling unit controls the supplying unit to put the first through the K-th arithmetic processors out of operation even upon production of the fault signal by any one of the first through the K-th arithmetic processors. Besides a first group of the first through the K-th arithmetic processors, a second group may be included in the computer system to comprise an additional arithmetic processor connected to the control section. When the memorizing unit memorizes the first information, the additional arithmetic processor is kept in operation. When the me…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.