IC chip having volatile memory cells simultaneously loaded with initialization data from uniquely associated non-volatile memory cells via switching transistors
US5230058A · kind A · utility
15Cited by
4References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 8, 1990 |
| Grant date | Jul 20, 1993 |
| Priority date | — |
| Expiry date | May 8, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4403
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Initial data and/or control bits of registers within a digital integrated circuit are simultaneously loaded from localized non-volatile memory cells provided as part of the circuit. Such loading is accomplished each time the circuit is initialized, such as when power is first turned on to a system in which the circuit is a part. An important use of this technique is with a computer peripheral circuit chip such as a serial communications controller.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.