CMOS delay line having duty cycle control
US5231320A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 18, 1992 |
| Grant date | Jul 27, 1993 |
| Priority date | — |
| Expiry date | Sep 18, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00195
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A delay line having feedback from a control circuit at the output of the delay line controls the delay line duty cycle to within a specified range. The delay line comprises at least one delay unit having control inputs to each delay unit. The output of the delay line feeds to a low-pass filter (LPF). A voltage proportional to the duty cycle of the delay line output is generated within the LPF and fed to a differential amplifier. The differential amplifier is in turn coupled to the control inputs of each of the delay units. When the voltage signal from the LPF is high (duty cycle is high), the differential amplifier will generate a signal causing the fall time of the signal propagating through the delay line to increase and rise time to decrease. This will decrease the high cycle time at the output of the delay line. When the voltage signal from the LPF is low (duty cycle is low), the differential amplifier will generate a signal causing the fall time to decrease and the rise time to increase. This will increase the high cycle time at the output of the delay line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.