Pulse width modulating producing signals centered in each cycle interval
US5231363A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 3, 1992 |
| Grant date | Jul 27, 1993 |
| Priority date | — |
| Expiry date | Aug 3, 2012 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/62
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pulse width modulating circuit including a shift register and a subtraction circuit, with first and second binary counters respectively connected to the outputs of the shift register and the subtraction circuit, and a logic circuit connected to the outputs of the binary counters. Pulse width control data bits are input to the shift register and the subtraction circuit. The shift register processes the pulse width control data bits by shifting them one bit to the right and dividing the control data bits in half. The output of the shift register is also connected to the subtraction circuit and provides one-half of the pulse width control data bits to the inputs of the subtraction circuit and the first counter. A load signal is respectively applied to the first and second binary counters which are responsive thereto for sensing the left and right edges of a pulse width modulation signal based upon the outputs from the shift register and the subtraction circuit. The pulse width modulation signal is located in the middle of the cycle interval as generated by the load signal. Pulse position correcting circuits may be interposed between the shift register and the first counter, and betw…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.