Technique for modifying an integrated circuit layout
US5231590A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 13, 1989 |
| Grant date | Jul 27, 1993 |
| Priority date | — |
| Expiry date | Oct 13, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/398
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An existing integrated circuit layout is modified or revised in order to shrink it, update it, modify it for merger with another circuit on a single chip, or the like, in a manner which assures, prior to implementing the modified layout in an integrated circuit chip, that the electronic circuit implemented by it has not inadvertently been modified in the process. Data of the existing layout is first run on a net list extractor computer software program in order to determine its net list. After the layout is modified by usual computer techniques, the modified layout data is run on the extractor program to obtain another net list, and the net lists are then compared for any undesired differences. Once the modified layout has been determined to be free of any such differences, a set of masks are made from the modified database. The masks are used then used to manufacture the integrated circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.