Scrambling/descrambling circuit
US5231667A · kind A · utility
10Cited by
5References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 4, 1991 |
| Grant date | Jul 27, 1993 |
| Priority date | — |
| Expiry date | Dec 4, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/582
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A scrambling/descrambling circuit that may be manufactured as a CMOS arrangement in LSI format and free of constraints on the degree of the generating polynomial involved. Scrambled (or descrambled) "m" bits of data output by registers are multiplied by multiplication circuits by a factor of the generating element .alpha..sup.m of the generating polynomial. The multiplied data are input back to the registers. The scrambled "m" bits of data are supplied to "m" exclusive-OR gates for exclusive-OR operation with input data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.