BICMOS output buffer noise reduction circuit
US5233237A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1991 |
| Grant date | Aug 3, 1993 |
| Priority date | — |
| Expiry date | Dec 6, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/09448
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A BICMOS output buffer circuit delivers output signals of high and low potential levels at an output (V.sub.OUT) in response to data signals at an input (V.sub.IN). A CMOS output pulldown driver transistor (Q60) sources base drive current to a relatively large current conducting bipolar primary output pulldown transistor (Q44). A relatively small current conducting CMOS secondary output pulldown transistor (Q60A) is coupled with primary current path in parallel with the primary current path of the bipolar primary output pulldown transistor (Q44) between the output (V.sub.OUT) and low potential power rail (GNDN). The control gate node of CMOS secondary output pulldown transistor (Q60A) is coupled to the control gate node of the CMOS output pulldown driver transistor (Q60) to initiate pulldown of a small sinking current before turn on of the bipolar primary output pulldown transistor (Q44) to reduce the maximum peak output noise (V.sub.OLP). A feed forward circuit capacitance is coupled between the control gate node of the CMOS output pulldown driver transistor (Q60) and base node of the bipolar output pulldown transistor (Q 44). The capacitance value is selected to pass a transient …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.