Video graphics display memory swizzle logic and expansion circuit and method
US5233690A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 1989 |
| Grant date | Aug 3, 1993 |
| Priority date | — |
| Expiry date | Jul 28, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G5/393
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit controls the reordering of data as it is transferred to control a memory. The data to be reordered is presented such that the ordinate bit position within a data word is uniquely associated with a particular input to a data bus. The bus inputs, however, are connected to the VRAM in an arrangement contrary to the desired ordinate association with the compressed data word. A single swizzle logic circuit operates to allow graphic compressed data to be reordered for presentation to the block-write inputs of a VRAM regardless of the VRAM or pixel size. The circuit relies upon properly expanding the compressed data prior to the actual reordering of the ordinate positions of the data bits. A method for controlling the reordering of data also is described.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.