Microprocessor with a reduced size microprogram
US5233695A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 16, 1990 |
| Grant date | Aug 3, 1993 |
| Priority date | — |
| Expiry date | Jul 16, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/223
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
When a data processing instruction is given to a microprocessor, and the code of a data register subject to designation is held in an instruction register, a first logic level is outputted from the instruction code decoder, but when the register subject to designation is the instruction queuing register in which a subsequent instruction code is to be held, a second logic level is outputted from the instruction code decoder. By the operation of logic switching means, when the first logic level is being outputted, the register select code decoder can select the data register designated, while when the second logic level is being outputted, the register select code decoder can select the instruction queuing register designated. Accordingly, this eliminates the necessity of carrying out the designation of a data register or queuing register in the microprogram, thus making it possible to reduce the size of the microprogram used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.