Memory with power supply intercept in redundancy logic
US5235548A · kind A · utility
16Cited by
9References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 12, 1990 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Jul 12, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A low-power SRAM with redundant rows in each of the subarrays. Conventional redundancy logic permits defective rows to be electrically replaced by redundant rows. In addition, power supply disconnect logic permits the V.sub.DD supply voltage line for the bad row to be disconnected.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.