Semiconductor device with apparatus for performing electrical tests on single memory cells
US5235549A · kind A · utility
9Cited by
8References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 23, 1991 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Dec 23, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having test circuitry incorporated into its design to enable direct external access to the bit lines of a single cell is described. When the device is put in test mode by applying external control signals, peripheral I/O circuitry is disabled. Once the I/O circuitry is disabled the test circuitry selects and enables the section of the array in which the selected cell is located through transfer circuits. The enabled transfer circuit for the selected section couples data between the selected cell and a set of predetermined I/O terminals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.