Memory addressing scheme
US5235551A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 8, 1991 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Jan 8, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0623
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for increasing the addressable memory space of an addressed line limited computer system. In the present invention, at least two memory planes, plane zero and plane one, are provided. Each memory plane contains the maximum number of addresses that can be addressed by the available address lines. The present invention constrains the starting addresses of individual character data that are valid in each memory plane. For example, if the addresses of the memory planes are configured in hexidecimal, memory plane zero contains valid starting addresses only at those locations having a least significant nibble of zero or eight. Memory plane one is constrained to have valid starting addresses, for example, at those addresses having a least significant nibble of "4" or "C". A processing means is provided to determine when a starting address is provided to the memory. The processor determines which memory plane can accept the starting address as a valid starting address and enables the address lines to communicate with that memory plane. More memory planes can be defined by reviewing more bits in the starting address. For example, if two bits are reviewed, four memory planes can be …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.