Time division multiplex voice data bus
US5235594A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 1991 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Aug 9, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M9/025
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
In a switching system for voice input/output devices, voice data is sampled, e.g., at an 8 KHz rate. To minimize overhead, the maximum number of devices in a system have a time slot for outputting data. Thus, the system operates at a system clock rate of 8 KHz times the maximum number of devices to be supported. In the illustrated embodiment, 768 devices are supported and thus the system operates at a 6.144 MHz clock rate. To enable such a large number of devices to be supported at a relatively slow clock rate, the data is transmitted in parallel. The switching system is constructed as N buckets or cabinets of M processing modules, each connected to J devices. A bus controller for each bucket connects the multiprocessing system bus in that bucket to intersystem buses connected to bus controllers in adjacent cabinets. Voice data samples are collected by a module collection bus and transferred to a bucket collection bus following data from any preceding buckets. When the final bus controller is reached, the collected voice data passes through a return bus which connects the bucket collection bus entering the final bus controller to a bucket distribution bus exiting the final bus cont…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.