Circuit arrangement for generating synchronization signals in a transmission of data
US5235596A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 16, 1991 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Jul 16, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0331
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
In a transmission of data upon employment of binarily coded data signals (D), reception clocks (ET) with which the data signals (D) are sampled in their middles are generated for the recovery of the transmitted data. The reception clocks (ET) are thereby synchronized phase-wise by the synchronization signals (SY) generated from the data signals (D). In order to also be able to sample the data signals (D) in their middles insofar as possible given distortions of the data signals (D) up to 50%, the synchronization signals (SY) are inventively generated taking the respective distortion into consideration. To this end, a counter (Z) is provided that is respectively counted from an initial value up to a final value by high-frequency clock pulses (T3). Given changes of the binary value of the data signals (D), a synchronization unit (SYS) sets the counter (Z) to its initial value. The counter (Z) is preceded by a switch unit (SS) that always through-connects clock pulses (T1) having a higher repetition rate whenever the counter (Z) has not yet reached its final value at the end of a data signal (D). An output unit (AS) always outputs a synchronization signal (SY) when the counter (Z) rea…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.