Synchronous/asynchronous I/O channel check and parity check detector
US5235602A · kind A · utility
11Cited by
7References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 11, 1991 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Jun 11, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved I/O channel check and parity check detector includes two similar detection paths each of which includes a check detector, a glitch reject circuit, and a read back register. A memory parity error causes a bit to be set in the read back register. An I/O channel check sets another bit in a read back register provided a memory parity error has not been signalled. If such signal occurs, the channel check is rejected. The read back bits are read through a port allowing the system to determine the source of error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.