Bus interface synchronization control system
US5235698A · kind A · utility
16Cited by
5References
13Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 12, 1989 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Sep 12, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The interface control system of this invention renders a high speed CPU compatible with low speed expansion devices such as expansion interfaces. The system causes the CPU clock signal to be in phase with the interface clock signal at the end of the last cycle of an interface cycle. At the end of the interface cycle, the system selects between a positive high speed and a negative high speed clock to be the CPU clock signal applied to the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.