Checkpointing mechanism for fault-tolerant systems
US5235700A · kind A · utility
93Cited by
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9Claims
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Key dates
| Filing date | Jan 16, 1991 |
| Grant date | Aug 10, 1993 |
| Priority date | — |
| Expiry date | Jan 16, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A device which switches data processing from an active processor, about to fail, to a back-up processor includes a memory change detector which captures memory changes in the memory of the active processor and a mirroring control circuit which causes the memory changes when committed by establishing recovery point signals generated by the active processor to be dumped into the memory of the back-up processor so that the back-up processor resumes operation of the active processor from the last established recovery point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.