Semiconductor memory circuit device and method for fabricating same
US5237187A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 27, 1991 |
| Grant date | Aug 17, 1993 |
| Priority date | — |
| Expiry date | Nov 27, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/31
Abstract
In a semiconductor memory circuit device wherein each memory cell is constituted by a series circuit of a memory cell selecting MISFET and an information storing capacitor of a stacked structure, there are present in a first region, which is a memory cell array region, a first MISFET having a gate electrode and source and drain regions; first and second capacitor electrodes and a dielectric film extended over a first insulating film and over the gate electrode; a second insulating film disposed on the second capacitor electrode; a third insulating film interposed between the first insulating film and first capacitor electrode; and a first wiring positioned on the second insulating film. In a second region of the device, which is a peripheral circuit region, there are present a second MISFET having a gate electrode and source and drain regions; a first insulating film on the gate electrode; a second insulating film on a third insulating film, the third insulating film being interposed between the first and second insulating films; and a second wiring on the second insulating film. The second wiring is formed by the same level conductor layer as that forming the first wiring. Similar…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.