High-speed CML push-pull logic circuit having temperature compensated biasing
US5237216A · kind A · utility
9Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 28, 1992 |
| Grant date | Aug 17, 1993 |
| Priority date | — |
| Expiry date | Apr 28, 2012 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00376
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A negative-phase output signal in an ECL circuit is extracted by an emitter-follower circuit, and the extracted signal is differentiated at its leading edge by a capacitor driven by the emitter-follower circuit so as to form a pulse wave, thus the differentiated signal drives a transistor connected in parallel with an emitter-follower resistor to which a positive-phase output signal is supplied. With this operation, a large amount of current flows only at the trailing edge of the output signal to shorten the fall time of the output from the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.